1. Field of the Invention
The present invention relates to an information processing apparatus, and a control method therefor, in particular, to a system including a programmable logic device.
2. Description of the Related Art
Various systems in each of which an FPGA (Field Programmable Gate Array) is mounted are proposed. For example, Japanese Patent Laid-Open No. 2010-049510 proposes a system configuration where one FPGA is mounted for each of a plurality of CPU modules existing in the system. If a high-performance FPGA is applied to the system configuration proposed in Japanese Patent Laid-Open No. 2010-049510, the cost becomes extremely high. To cope with this, a system configuration is considered where two or more CPUs share one FPGA by using the FPGA that has a plurality of high-speed ports (for example, PCI Express) to which the CPUs are connectable (to be referred to as an “FPGA sharing configuration” hereinafter).
On the other hand, Japanese Patent Laid-Open No. 2013-098823 discloses, as an FPGA configuration method, a new method different from a conventional method of loading configuration data from a ROM. The disclosed method is a method of loading the configuration data from an HDD to an FPGA by using a CPU as a master device (to be referred to as a “CPU master configuration” hereinafter). With the CPU master configuration, the processing contents of the FPGA can be updated only by replacing and loading a file in the HDD without rewriting the ROM.
In the case of a general FPGA device, there is only one high-speed port corresponding to the CPU master configuration. That is, even if two or more CPUs are connected to the FPGA as in the FPGA sharing configuration, there is only one CPU which becomes a master device for a configuration. In this case, the CPU other than the master device cannot execute the configuration, resulting in the need to request the configuration for a master device CPU. However, if such a configuration request process is incorporated in software, a software configuration becomes complicated for the reason of occurrence of inter-CPU communication or the like, and it will take time before a request source CPU starts using the FPGA.